With the development of a series of resolution enhancement techniques (RETs), such as optical proximity correction (OPC) and multiple patterning, wafer pattern distortions during lithography process can be effectively alleviated in the advanced nanometer technologies. However, due to process variation (PV) in the lithography process, such as dosage error and defocus, deviation of critical circuit features may occur under different PV conditions. Especially in analog integrated circuits (ICs), such deviation might introduce device mismatch on sensitive analog blocks, and in turn degrade circuit performance.
Conventional PV-aware OPC methods [Su et al. 2016] attempted to shrink the possible wafer image range under PV conditions. In the literature, most of the existing studies on OPC are only focused on digital IC layouts, which are usually more compact compared to the analog counterpart. Those digital OPC solutions, which are fairly general for fixing pattern distortions, can hardly be applied to a complex mixed-signal IC chip enclosing high-performance analog blocks. Therefore, a unique OPC solution to analog layouts with specific optimization objectives and higher efficiency is demanded due to the following particularity of analog layouts: 1) various pattern manipulation can be performed by leveraging the available space within analog layouts; 2) mismatch effects induced under PV conditions may have stronger negative impact on analog layout constraints, such as matching and symmetry, which require dedicated handling; and 3) pattern distortions may readily change device sizes that actually dominantly determine the analog circuit performance. Therefore, a standalone generic OPC process may not be sufficient for analog circuit performance preservation. In this context, a circuit sizing method along with proper PV considerations would be highly essential to reduce the analog circuit vulnerability to mismatch effects.
Evolutionary algorithm (EA) is a popular circuit sizing scheme, which attempts to find the global optimal circuit sizes by inheriting elite genes from previous generations. Due to its mutation and crossover strategies, EA presents a superior ability of escaping from local optimal points in the highly non-linear solution space. However, the EA-based sizing method is very time-consuming because it usually requires large population and generation sizes. Especially when post-layout effects, e.g., PV-aware pattern distortions, are considered during the calculation of sizing fitness, a layout synthesis has to be performed on each individual within each population, which may significantly degrade the algorithmic efficiency. Compared to the stochastic EA-based sizing approaches, Antreich et al. [2000] proposed a deterministic circuit sizing algorithm, which can solve the sizing problem much faster. With appropriate linearized approximations, this algorithm explores the solution space along a specific direction based on circuit performance gradients in order to reach an optimal set of circuit sizes. As long as a reasonably suitable initial sizing solution is available, this deterministic sizing method would converge quickly, which can offer high efficiency and applicability even when the time-consuming layout synthesis is required for post-layout effect considerations during the sizing process.
Analog layout synthesis, such as analog layout retargeting, acts as a bridge between pre-layout circuit design stage and post-layout effects. By using an effective layout synthesis scheme, the circuit sizing algorithms can thoughtfully handle the post-layout effects and in turn benefit the chip yield. Since both circuit sizing and layout synthesis might be slow processes, the combination of the deterministic circuit sizing algorithm and the layout retargeting platform could be a good candidate for lithography-aware optimizations. As Liu and Zhang [2010] proposed, a graph-based analog layout retargeting approach can quickly compose a target layout by inheriting knowledge from a legacy layout and also imposing new circuit sizes, constraints and specifications.